nSys Verification Suite (nVS) family is the world's largest portfolio of Verification IPs.
Hundreds of ASIC/FPGA developers worldwide are using the nVS family & benefit from
the widely accepted & proven Verification IPs for standard interfaces / protocols.
Every nVS consists of BFMs, Monitors, Assertions-based Checkers and Test Suites
which enables users to quickly build environments to verify their designs.
