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vSync Circuits delivers a complete solution for synchronization failures problem in multiple clock domain designs. Unlike typical clock domain crossing (CDC) verification tools, vSync Circuits suite focuses on providing the correct solutions, rather than merely pointing at the problems.
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Products:
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- vGenerator – Synchronization glue logic generator which offers a variety of synchronization solutions for different system requirements. The vGenerator EDA tool generates and customizes reliable synchronization solutions for each interface and each clock domain crossing.
- Guides the user through the requirement specification
- Supports different interface protocols
- Generates multiple reliable synchronization solutions and suggests the preferred one
- Generates simulation models for the chosen solution
- Generates synthesis constraints
- Contains rich IP data base with different synchronization solutions:
- Point-to-point, vNoC, Reset synchronization, Clock gating and switching
- Supports different operating conditions
- Supports multiple FPGA design flows:
- Xilinx (ISE and Synplify)
- Altera (Quartus II and Synplify)
- Lattice (ispLEVER)
- Actel (Libero)
- Aldec
- Supports multiple ASIC design flows:
- Synopsys (DC), Cadence
- Can be tuned for a specific ASIC technology
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- vChecker – Clock Domain Crossing (CDC) static analysis and CDC management tool. vChecker EDA tool analyzes a design for synchronization failures.
- Applied at Register Transfer Level (RTL) and/or at Gate Level (GL)
- Supports VHDL, Verilog and SystemVerilog
- Guides the user through the entire analysis process
- Identifies clock domain crossings
- Classifies clock domain crossing into two groups of correctly and incorrectly synchronized crossings
- Identifies well-known synchronizers
- Identifies and verifies Vendor (Altera/Synopsys/Xilinx) synchronizers
- Identifies synchronizers generated by vGenerator
- Identifies and verifies asynchronous resets
- Grades design reliability
- Suggests correct solutions for identified incorrect clock domain crossings (a link to vGenerator)
- Supports different operating conditions
- Has a graphical interface for clock domain crossing exploration
- Directly links to the RTL code through built in text editor
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