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ASIC
EDA
Avionics Certification
Resource Management
Automatic Testing for Embedded Software
Design Verification & Optimization
RTL Simulation & Verification
RTL Simulation & Acceleration
Emulation & Prototyping
Design For Test (DFT)
IT/CAD Infrastructure and Services
HDL Front - End
Clock Domain Crossing (CDC) Verification

 
 
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Design Verification & Optimization

Design Verification & Optimization

AST's Design Verification & Optimization solutions support new technologies, methodologies and products which speed up overall design verification and optimization processes and reduce their complexities.

We offer unique methodologies, incorporating electronic system level design, coverage-driven verification, assertion-based-verification, HDL linting, and code analysis.

Our solutions automate RTL and memory power optimization. We are able to reduce power up to 60%  with little or no impact to timing or area.

We provide the Analog FastSPICE™ Platform (AFS), the industry’s single unified verification platform for analog, RF, and mixed-signal design. AFS provides indistinguishable results to customary SPICE 5x-10x faster single-core and up to 50x faster characterization with multi-core parallel operating mode.  AFS handles circuits with up to 10 million elements, and obtains the only nanometer SPICE accurate device noise analysis.
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