PowerPro CG Automated RTL Power Optimization Solution. It has reduced power by up to 60% in customers RTL designs.

PowerPro MG Reduces Dynamic and Leakage Power in Memories.

SLEC comprehensively proves functional equivalence between reference and implementation models.

SLEC SYSTEM verifies that RTL implementations match hardware intent captured in system-level models written in SystemC and C++

SLEC RTL verifies that RTL (Verilog and VHDL) optimizations for power, timing and area do not introduce functional defects.

SLEC CG verifies block-level clock gating changes in Verilog and VHDL designs.

For more information please contact:

Orly Ellison

AST Marketing Manager

orly@ast.co.il