ClioSoft, Inc ., developer of the premier hardware configuration management (HCM) system for the electronics design industry, has selected Advanced Semiconductor Technology Ltd. (AST) to be its exclusive distributor and technical representative in Israel

 
 
AST and ALDEC are at DAC 2010 in Anaheim California
 
PLX Technology, Inc. (NASDAQ: PLXT), today announced its unique USB Duet® solution for mobile PCs enables plug-and-play connectivity with the Apple® iPad™ tablet
 
Calypto® Design Systems Inc., the leader in sequential analysis technology, today announcedthat the Semiconductor Technology Academic Research Center (STARC) has adopted Calypto’s PowerPro MG product for their STARCAD-CEL Version 4.0 design flow
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Products » ASIC » IP Development

 

Sometimes a special requirement for an IP is needed. Our experienced design team can design your IP for you, either in synthesizable VHDL or VERILOG or in hard GDS II core for your selected process. We can provide you with both FPGA implementation and/or Shuttle Silcon implementation for validation in your design.
AST has developed several off the shelf IP’s for Encryption and a powerful customizable DSP core:

AST's IP Cores

DESEncryption/Decription Core

The core is a DES Standard compliant, VHDL based design that can be implemented as the basic DES core, with the CBC mode added and/or in the Triple DES mode. The design is also available in gate level, synthesized to any technology supported by Synopsys DC. This is a very efficient design requiring only 900 gates for the basic core and able to process 800Mb/sec in a typical 0.35u CMOS Process.
Click here for our full preliminary spec.

Customizable DSP core - CDSPtm

The CDSPtm is a general purpose, high performance customizable fixed-point DSP core featuring high execution speeds for both signal-processing algorithms and standard microprocessor applications. It is meant to be used as an embedded cell in ASIC's developed on most of the current 0.6u and below technologies. It is highly customizable and can be targeted at a large number of technologies thanks to its parameterized, HDL-only based design.

The CDC-XP can be optimized for most of the common DSP algorithms to obtain a highly efficient, low power and small area implementation. It is therefore most suitable for low-cost, high-volume applications.
Click here for our preliminary spec.

 AST’s Mixed Signal IP’s

AST cASIC Israel ooperates with Moscad Consulting of Le Vaud, Switzerland in its Mixed Signal IP development.  Moscad Consulting has accumulated over 20 years of expertise in Mixed Signal design and development. 

AST and Moscad share a portfolio of  Analog  IP's such as Voltage Regulators, Voltage Detectors, Band Gap References, Special IO’s, Asynchronous RAM’s, Clock Generators, DA and AD Converters and more.

These IP's have been developed for the leading foundries such as TSMC, UMC and CSM as well as proprietary customer processes.

AST and Moscad are also capable of offering custom developed Mixed Signal IP's at attractive prices with fast turnaround in a wide range of technologies.

 


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