Verific
Source code (C++) Verilog, SystemVerilog and VHDL front-ends (parsers, analyzers, elaborators) as well as a generic hierarchical netlist database for EDA applications.
HDL Source Code Components
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System Verilog 3.1 and 3.2 parser, analyzer, and elaborator
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Verilog IEEE 1364-1995/2001 pre-processor, parser, analyzer, and elaborator
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Verilog-AMS parser and analyzer
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VHDL IEEE 1076-1993 parser, analyzer, and elaborator
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PSL/SUGAR parser and analyzer for VHDL and Verilog
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Automatic FSM/RAM extraction from RTL
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EDIF 2.0 Reader
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SDF Reader
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Liberty Reader
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Hierarchical, technology independent database