Active-HDL is an integrated, easy-to-use RTL design and simulation solution, providing a robust design creation tool suite, a high-performance
mixed-language simulator and a multi-vendor FPGA Flow manager that controls Simulation, Synthesis and Implementation for FPGAs and popular EDA tools, in a single environment.
Language Support: VHDL, Verilog®, SystemVerilog (Design), SystemC, Assertions (SVA, PSL and OVA) and EDIF
Riviera-PRO is a common-kernel, mixed-language, multi-platform simulator for VHDL, Verilog®, SystemVerilog, SystemC/C/C++ and
Assertion-Based Verification (ABV). Riviera-PRO works in a command-line mode for maximum speed and includes enhanced editing,
tracing, debugging and code coverage. It supports System Level Verification with SystemC and SystemVerilog, Electronic System Level
(ESL), Transaction Level Modeling (TLM), Open Verification Methodology (OVM) and Verification Methodology Manual (VMM).
Language Support: VHDL, Verilog®, SystemVerilog (Design, Verification, Assertions), SystemC/C/C++, PSL/OVA Assertions and EDIF.
ALINT™ Design Rule Checking
ALINT is a design analysis software tool for fast examination of HDL source code of complex ASIC, FPGA and SOC designs. ALINT checks
VHDL, Verilog and mixed-language HDL code against industry standard design rules. It detects such problems as poor coding styles,
improper clock and reset management, simulation and synthesis problems, poor testability and source code issues throughout the
design flow. Application: ASIC, FPGA and SOC designs Language Support: VHDL, Verilog® and/or mixed-language.
HES™ Hardware Emulation System
HES is a patented Hardware-Assisted Verification solution, which can be used for Emulation, Acceleration and Prototyping. HES can
handle large, complex ASIC and SOC designs. It includes Transaction Level Modeling (TLM) with SCE-MI 2.0 for high-performance
emulation and prototyping from 1 MHz to 100 MHz, using off-the-shelf boards. The acceleration mode feeds selected test points from
hardware into waveform viewers of leading simulators including Riviera-PRO™, VCS®, NC-Sim®, ModelSim®, Active-HDL™ and can
accelerate simulation performance 10x or more. Application: ASIC, FPGA, SOC, CPLD and PLD designs Language Support: VHDL,
Verilog®, EDIF and SystemC/C/C++.
Military and Aerospace Solutions
Aldec DO-254/CTS provides 100% Functional Verification coverage, tool assessment and design requirements traceability in software and
hardware. DO-254/CTS supports the “Design Assurance Guidance for Airborne Electronic Hardware” (DO-254/ED80) chapter 6.2
“Verification Process” and chapter 11.4 “Tool Assessment and Qualification Process”. It is a patented solution for ultra-fast and reliable
verification of devices for assurance levels A, B, C and D.
Using Flash-based Actel ProASIC®3E FPGA technology, the Aldec Prototype Adaptor allows on-the-fly re-programming of Actel RTAX-S/SL
or RTSX-SU anti-fuse devices, used for space-flight systems. The prototyping adaptor supports RTSX-SU and RTAX-S/SL devices with up to
4000S in capacity and packages CQ208, CQ256, CQ352 and CG624. This one-of-a-kind solution greatly simplifies the prototyping process,
shortens design cycles and reduces project/chip purchase costs.