Aldec-Aldec, Inc., a leader in mixed RTL simulation and verification, announces support for the VHDL IEEE 1076™-2008 standard. 

Alvand
- Faraday Selects Alvand Technologies AFE (Analog Front End) IP
 to Support Next Generation Wireless Applications.

 
Calypto® Design Systems Inc., the leader in sequential analysis technology, today announcedthat the Semiconductor Technology Academic Research Center (STARC) has adopted Calypto’s PowerPro MG product for their STARCAD-CEL Version 4.0 design flow

 

 

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The Design Verification Company!
Active-HDL is a completely integrated FPGA design and simulation environment for VHDL, Verilog, C/C++ and EDIF from design entry through implementation.  Active-HDL provides the fastest simulation runs for all designs, regardless of source language or target silicon, including those with embedded devices. CoVer is a hardware/software co-verification platform allowing hardware engineers and software developers to work in parallel.
Riviera is a high-performance ASIC and large FPGA verification solution. Aldec has also released a hardware accelerator, Riviera-IPT that speeds Riviera.                                                                         

   
 

Alvand Technologies offers best-in-class analog/digital converters (ADC/DAC) and Analog Front End (AFE) technologies in advanced deep-submicron manufacturing, available in 40nm, 65nm, 90nm, 130nm and 180nm process nodes at TSMC and UMC. Alvand's ADC/DAC and AFE IP cores have been licensed by over a dozen customers and have been productized in over eighteen devices currently shipping in mass production. Alvand differentiates its high-performance IP cores.

 

PowerPro Clock Gating is an Automated RTL Power Optimization Solution. It has reduced power by up to 60% in customers RTL designs.

SLEC comprehensively proves functional equivalence between reference and implementation models.

SLEC SYSTEM verifies that RTL implementations match hardware intent captured in system-level models written in SystemC and C++

SLEC RTL verifies that RTL (Verilog and VHDL) optimizations for power, timing and area do not introduce functional defects
SLEC CG verifies block-level clock gating changes in Verilog and VHDL designs.

   
   ClioSoft's SOS Design Data Collaboration Platform enables efficient management of design data from concept through tape-out and improves global team productivity.
The SOS platform gives design teams the freedom and flexibility to choose the way they work, share and collaborate.Custom engineered adaptors seamlessly integrate SOS with leading design flows:
·        Cadence Virtuoso® Custom IC
·        Synopsys Custom Designer
·        Mentor ICstudio
SpringSoft Laker

 

   
HighRely is a leader in providing highly reliable embedded solutions. HighRely provides engineering services forcritical embedded products including application design, development, testing, project management, and certification. Our engineer's solutions are in many medical devices, jets, satellites, defense, nuclear, and transportation based embedded devices
 
   
Helion Technology is a specialist provider of data security and encryption IP, offering an extensive range of innovative and product-proven security cores, backed by expert design services and support capabilities. Helion’s broad range of IP cores aims to offer a choice for any specific application, so that the solution can very closely fit the requirement. This choice allows logic area and performance to be traded as needed. Helion also places a great emphasis on high performance solutions in FPGA, with carefully optimized IP cores available which achieve ASIC-like results. Helion offer a flexible and friendly approach, plus a willingness to go the extra mile to get the very best solution for its customers.
   
Providing standard software configuration management (SCM) functionality on an
advanced modular platform that enables hardware design methodologies in a
version-controlled context, the new Methodics solution represents a revolutionary
approach to global design collaboration.
   
nSys Verification Suite (nVS) family is the world's largest portfolio of Verification IPs.
 Hundreds of ASIC/FPGA developers worldwide are using the nVS family & benefit from
the widely accepted & proven Verification IPs for standard interfaces / protocols.
 Every nVS consists of BFMs, Monitors, Assertions-based Checkers and Test Suites
which enables users to quickly build environments to verify their designs
 

Flow management and network (grid) computing solutions for EDA environments.
Runtime Design Automation provides the leading IC design Flow automation tools, Flowtracer/EDA and Flowtracer/NC, to manage all your design bandwidth - staff, licenses, and CPUs, with a single toolset. Flowtracer tracks all the compute jobs in your project, and automatically runs them in the right order, in parallel across your network, with one-click simplicity.
Typically speedup in the execution of each design flow by a factor of 10x to 20x in a variety of application areas including regression testing, test vector design, standard cell library characterization, software builds, HDL based design.

 

 

 
 
D&R Enterprise Platform for Internal and External IPs management aims at covering a large
spectrum of information and data sharing needs in Electronic Systems Design such as
internal design reuse, external product cataloguing and license management, configurable
documentation center, web support etc…
 
This innovative platform based on the latest Java/XML technology has proven a fascinating
design information sharing efficiency. It yields increasing system design productivity as well
as outstanding improvements in supplier product management.
 

The Leading Worldwide Independent Provider of EDA solutions! Markets industry-leading products that enable IC engineers to quickly and more accurately complete their designs.
Bantam, a product of Saratoga Data Systems, reads the de facto industry standard file format for representing IC designs, GDSII Stream, restructures it and writes a significantly smaller, but functionally equivalent, GDSII Stream file.
HyperPlot Solutions, a product of PINEBUSH Technologies, represents the standard for printing and plotting in the semiconductor (EDA) industry.

 

Sigrity develops advanced software analysis solutions to ensure power integrity and signal integrity in chips,
packages and printed circuit boards, Sigrity also develops physical design tools for single die and SiP implementations.
190+ Sigrity customers use our software for a variety of high performance IC package and printed circuit board applications
addressing the needs of design analysis across silicon-package-board. IC package physical design software speeds the
implementation of single die designs as well as SiP and PoP implementations.
   

The only DFT (DesignForTest) company!
SynTest provides customers with the highest quality and most advanced IC Test and Fault Simulation solutions and Services, backed by the most dedicated support team in the industry.
SynTest products include: TurboScan - Scan Insertion and ATPG, TurboBist –Logic Bist and Memory Bist, TurboFault – The fastest Fault Simulator on the market. TurboDFT – DFT Design Rule Check and TurboBSD - Boundary Scan and JTAG tool. SynTest tools are supported by AST’s 10 years of experience in DFT.

 

 

 

Source code (C++) Verilog, SystemVerilog and VHDL front-ends: parsers, analyzers, elaborators as well as a generic hierarchical netlist database for EDA applications.
verific provides also complete test suites covering Verilog, System Verilog amd VHDL Many EDA and semiconductor companies worldwide are shipping products incorporating Verific's technology, with a combined customer base of over 20,000 users.

 

 

                                                                          

 

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