AST has a line of Analog IP’s developed in partnership with Moscad Design Automation, a line of special purpose Digital IP’s and a Constraints Management Toolset available under a site license and support arrangement.
Digital IP’s:
CDSP - Customizable DSP Core:
The CDSP is a general purpose, high performance customizable fixed-point DSP core featuring high execution speeds for both signal-processing algorithms and standard microprocessor applications. It is meant to be used as an embedded cell in ASIC’s developed on most of the 0.18u and below technologies. It is highly customizable and can be targeted at a large number of technologies thanks to its parameterized, HDL-only based design.
The CDSP can be optimized for most of the common DSP algorithms to obtain a highly efficient, low power and small area implementation. It is therefore most suitable for low-cost, high-volume applications.
A number of productivity tools have been developed to ease the elaboration/deploying of DSP applications on the CDSP. These include an Assembly Language Integrated Development Environment (aIDE) and a collection of standard DSP functions (CDSPLib). A K&R C Language Integrated Development Environment (cIDE) is currently under development.
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DES - Data Encryption Standard:
The core is a DES compliant, VHDL based design that can be implemented as the basic DES core, with the CBC mode added and/or in the Triple DES mode. The design is also available in gate level, synthesized to any technology supported by Synopsys DC. This is a very efficient design requiring only 900 gates for the basic core and able to process 800Mb/sec in a typical 0.25u CMOS Process.
For more information check here: DES Core
LVDS RX/TX:
This is a Silicon Proven LVDS Receiver Transmitter I/O cell for UMC LG180 process.
For more information check here: LVDS
Software IP’s
CMT Toolset:
One of the challenges of ASIC design is managing the timing constraints throughout the various steps of the design and implementation phases: from RTL through logic synthesis, P&R, Signal-Integrity and to sign-off STA.
The timing constraints are usually derived from the system requirements and are documented in a Device Specification. The Design Specifications has to be translated into a set of timing constraint TCL commands. The TCL scripts are used for Synthesis, P&R and Timing Sign-Off by the implementation/verification tools. The constraints are usually written and handled using long and complicated TCL scripts, and only the designer who wrote them can really understand what is going on there. Additionally, there’s no standard in the industry for design constraining, therefore designers from different groups/companies working together on the same project may have misunderstandings and/or gaps in the timing coverage of the design.
Our solution, called Constraint Management Toolset (CMT), supports the constraint management from the Design Specification through all the design implementation phases to the STA results presentation and review. We are using the highest level of data, such as oscillator frequency, duty cycle, jitter etc. directly from the Design Specification. This data is managed in a worksheet template, which is very friendly and easy to update and review. CMT automatically generates TCL scripts, creating clock definitions, domain relationships, interface timing constraints, mode definitions and exceptions (false path, multi-cycle etc.).